TY - JOUR
T1 - A custom interconnection multi-FPGA framework for distributed processing applications
AU - Salazar-Garcia, Carlos
AU - Chacon-Rodriguez, Alfonso
AU - Rfmolo-Donadfo, Renato
AU - Garcia-Ramirez, Ronny
AU - Solorzano-Pacheco, David
AU - Gonzalez-Gomez, Jeferson
AU - Strydis, Christos
N1 - Publisher Copyright:
©2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The development of multi-FPGA systems focused on high-performance computing requires high-speed channels, low bandwidth overhead and latency. In this paper, we propose a multi-FPGA interconnection framework aimed at distributed processing applications. Our solution allows efficient communication between different processing elements distributed among the FPGAs. To evaluate our proposal, we built a multi-FPGA system composed of five Zynq ZC706 FPGA boards capable of hosting a diverse number of coprocessors distributed over our custom network. With an aggregate bandwidth of up to 25Gbps per FPGA board, the interconnection framework reaches a latency of only 200.36ns, one of the lowest reported in the lElectronics Engineering, iterature. Experimental results show a computational efficiency of 97.25 % with a sustained throughput of 21.4GFLOPS. Furthermore, the proposed network interconnection architecture is easily portable to the latest generation FPGAs. This makes the current proposal a competitive option for distributed processing in multi-FPGA systems.
AB - The development of multi-FPGA systems focused on high-performance computing requires high-speed channels, low bandwidth overhead and latency. In this paper, we propose a multi-FPGA interconnection framework aimed at distributed processing applications. Our solution allows efficient communication between different processing elements distributed among the FPGAs. To evaluate our proposal, we built a multi-FPGA system composed of five Zynq ZC706 FPGA boards capable of hosting a diverse number of coprocessors distributed over our custom network. With an aggregate bandwidth of up to 25Gbps per FPGA board, the interconnection framework reaches a latency of only 200.36ns, one of the lowest reported in the lElectronics Engineering, iterature. Experimental results show a computational efficiency of 97.25 % with a sustained throughput of 21.4GFLOPS. Furthermore, the proposed network interconnection architecture is easily portable to the latest generation FPGAs. This makes the current proposal a competitive option for distributed processing in multi-FPGA systems.
UR - http://www.scopus.com/inward/record.url?scp=85141705668&partnerID=8YFLogxK
UR - https://ieeexplore-ieee-org.tudelft.idm.oclc.org/stamp/stamp.jsp?tp=&arnumber=9893238
U2 - 10.1109/SBCCI55532.2022.9893238
DO - 10.1109/SBCCI55532.2022.9893238
M3 - Conference article
AN - SCOPUS:85141705668
JO - SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)
JF - SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)
T2 - 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022
Y2 - 22 August 2022 through 26 August 2022
ER -