A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink

P. Guo; Z. Y. Chang; E. Noothout; H. J. Vos; J. G. Bosch; N. De Jong; M. D. Verweij; M. A.P. Pertijs

doi:10.23919/VLSITechnologyandCir57934.2023.10185159

A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink

P. Guo^*, Z. Y. Chang, E. Noothout, H. J. Vos, J. G. Bosch, N. De Jong, M. D. Verweij, M. A.P. Pertijs

^*Corresponding author for this work

Cardiology

Research output: Chapter/Conference proceeding › Conference proceeding › Academic › peer-review

2 Citations (Scopus)

Abstract

This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming (μ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The μ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.

Original language	English
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863488069
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185159
Publication status	Published - 24 Jul 2023
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: 11 Jun 2023 → 16 Jun 2023

Publication series

Series	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2023-June
ISSN	0743-1562

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	11/06/23 → 16/06/23

Bibliographical note

Funding Information:
Acknowledgement This publication is part of the project MIFFY with project number 15293 of the Open Technology Programme which is financed by the Dutch Research Council (NWO).

Publisher Copyright:
© 2023 JSAP.

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10.23919/VLSITechnologyandCir57934.2023.10185159

Cite this

Guo, P., Chang, Z. Y., Noothout, E., Vos, H. J., Bosch, J. G., De Jong, N., Verweij, M. D., & Pertijs, M. A. P. (2023). A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185159

Guo, P. ; Chang, Z. Y. ; Noothout, E. et al. / A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink. 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology, Vol. 2023-June).

@inproceedings{ee4c638ed9534951a5ebd5c87cf78c71,

title = "A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink",

abstract = "This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming (μ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The μ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.",

author = "P. Guo and Chang, {Z. Y.} and E. Noothout and Vos, {H. J.} and Bosch, {J. G.} and {De Jong}, N. and Verweij, {M. D.} and Pertijs, {M. A.P.}",

note = "Funding Information: Acknowledgement This publication is part of the project MIFFY with project number 15293 of the Open Technology Programme which is financed by the Dutch Research Council (NWO). Publisher Copyright: {\textcopyright} 2023 JSAP.; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

month = jul,

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doi = "10.23919/VLSITechnologyandCir57934.2023.10185159",

language = "English",

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Guo, P, Chang, ZY, Noothout, E, Vos, HJ , Bosch, JG , De Jong, N , Verweij, MD & Pertijs, MAP 2023, A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., Digest of Technical Papers - Symposium on VLSI Technology, vol. 2023-June, 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 11/06/23. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185159

A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink. / Guo, P.; Chang, Z. Y.; Noothout, E. et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Digest of Technical Papers - Symposium on VLSI Technology, Vol. 2023-June).

Research output: Chapter/Conference proceeding › Conference proceeding › Academic › peer-review

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AU - Guo, P.

AU - Chang, Z. Y.

AU - Noothout, E.

AU - Vos, H. J.

AU - Bosch, J. G.

AU - De Jong, N.

AU - Verweij, M. D.

AU - Pertijs, M. A.P.

N1 - Funding Information: Acknowledgement This publication is part of the project MIFFY with project number 15293 of the Open Technology Programme which is financed by the Dutch Research Council (NWO). Publisher Copyright: © 2023 JSAP.

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N2 - This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming (μ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The μ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.

AB - This paper presents a pitch-matched transceiver ASIC integrated with a 2-D transducer array for a wearable ultrasound device for transfontanelle ultrasonography. The ASIC combines 8-fold multiplexing, 4-channel micro-beamforming (μ BF) and sub-array-level digitization to achieve a 128-fold channel-count reduction. The μ BF is based on passive boxcar integration and interfaces with a 10-bit 40 MS/s SAR ADC in the charge domain, thus obviating the need for explicit anti-alias filtering and power-hungry ADC drivers. A compact and low-power reference generator employs an area-efficient MOS capacitor as a reservoir to quickly set a reference for the ADC in the charge domain. A low-power multi-level data link concatenates outputs of four ADCs, leading to an aggregate 3.84 Gb/s data rate. Per channel, the RX circuit consumes 2.06 mW and occupies 0.05 mm2.

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M3 - Conference proceeding

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BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

PB - Institute of Electrical and Electronics Engineers Inc.

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Guo P, Chang ZY, Noothout E, Vos HJ , Bosch JG , De Jong N et al. A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Digest of Technical Papers - Symposium on VLSI Technology, Vol. 2023-June). doi: 10.23919/VLSITechnologyandCir57934.2023.10185159

A Pitch-Matched Transceiver ASIC for 3D Ultrasonography with Micro-Beamforming ADCs based on Passive Boxcar Integration and a Multi-Level Datalink

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