A probabilistic analysis of resilient reconfigurable designs

A. Malek*, S. Tzilis, D. A. Khan, I. Sourdis, G. Smaragdos, C. Strydis

*Corresponding author for this work

Research output: Chapter/Conference proceedingConference proceedingAcademicpeer-review

3 Citations (Scopus)

Abstract

Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising a System-on-Chip can be partitioned into a handful of substitutable units interconnected with reconfigurable wires to allow isolation and replacement of faulty parts. This paper offers a probabilistic analysis of reconfigurable designs estimating for different fault densities the average number of fault-free components that can be constructed as well as the probability to guarantee a particular availability of components. Considering the area overheads of reconfigurability, we evaluate the resilience of various reconfigurable designs with different granularities. Based on this analysis, we conduct a comprehensive design-space exploration to identify the granularity mixes that maximize the fault-tolerance of a system. Our findings reveal that mixing fine-grain logic with a coarse-grain sparing approach tolerates up to 3× more permanent faults than component redundancy and 2× more than any other purely coarse-grain solution. Component redundancy is preferable at low fault densities, while coarse-grain and mixed-grain reconfigurability maximize availability at medium and high fault densities, respectively.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages141-146
Number of pages6
ISBN (Electronic)9781479961559
DOIs
Publication statusPublished - 18 Nov 2014
Event27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014 - Amsterdam, Netherlands
Duration: 1 Oct 20143 Oct 2014

Publication series

SeriesProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN1550-5774

Conference

Conference27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014
Country/TerritoryNetherlands
CityAmsterdam
Period1/10/143/10/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

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