A probabilistic analysis of resilient reconfigurable designs

A. Malek; S. Tzilis; D. A. Khan; I. Sourdis; G. Smaragdos; C. Strydis

doi:10.1109/DFT.2014.6962074

A probabilistic analysis of resilient reconfigurable designs

A. Malek^*
, S. Tzilis
, D. A. Khan
, I. Sourdis
, G. Smaragdos
, C. Strydis

^*Corresponding author for this work

Neurosciences

Chalmers University of Technology

Research output: Chapter/Conference proceeding › Conference proceeding › Academic › peer-review

3 Citations (Scopus)

Abstract

Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising a System-on-Chip can be partitioned into a handful of substitutable units interconnected with reconfigurable wires to allow isolation and replacement of faulty parts. This paper offers a probabilistic analysis of reconfigurable designs estimating for different fault densities the average number of fault-free components that can be constructed as well as the probability to guarantee a particular availability of components. Considering the area overheads of reconfigurability, we evaluate the resilience of various reconfigurable designs with different granularities. Based on this analysis, we conduct a comprehensive design-space exploration to identify the granularity mixes that maximize the fault-tolerance of a system. Our findings reveal that mixing fine-grain logic with a coarse-grain sparing approach tolerates up to 3× more permanent faults than component redundancy and 2× more than any other purely coarse-grain solution. Component redundancy is preferable at low fault densities, while coarse-grain and mixed-grain reconfigurability maximize availability at medium and high fault densities, respectively.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	141-146
Number of pages	6
ISBN (Electronic)	9781479961559
DOIs	https://doi.org/10.1109/DFT.2014.6962074
Publication status	Published - 18 Nov 2014
Event	27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014 - Amsterdam, Netherlands Duration: 1 Oct 2014 → 3 Oct 2014

Publication series

Series	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN	1550-5774

Conference

Conference	27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014
Country/Territory	Netherlands
City	Amsterdam
Period	1/10/14 → 3/10/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

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10.1109/DFT.2014.6962074

Cite this

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abstract = "Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising a System-on-Chip can be partitioned into a handful of substitutable units interconnected with reconfigurable wires to allow isolation and replacement of faulty parts. This paper offers a probabilistic analysis of reconfigurable designs estimating for different fault densities the average number of fault-free components that can be constructed as well as the probability to guarantee a particular availability of components. Considering the area overheads of reconfigurability, we evaluate the resilience of various reconfigurable designs with different granularities. Based on this analysis, we conduct a comprehensive design-space exploration to identify the granularity mixes that maximize the fault-tolerance of a system. Our findings reveal that mixing fine-grain logic with a coarse-grain sparing approach tolerates up to 3× more permanent faults than component redundancy and 2× more than any other purely coarse-grain solution. Component redundancy is preferable at low fault densities, while coarse-grain and mixed-grain reconfigurability maximize availability at medium and high fault densities, respectively.",

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Malek, A, Tzilis, S, Khan, DA, Sourdis, I, Smaragdos, G & Strydis, C 2014, A probabilistic analysis of resilient reconfigurable designs. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 6962074, Institute of Electrical and Electronics Engineers Inc., Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 141-146, 27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, Netherlands, 1/10/14. https://doi.org/10.1109/DFT.2014.6962074

A probabilistic analysis of resilient reconfigurable designs. / Malek, A.; Tzilis, S.; Khan, D. A. et al.
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 2014. p. 141-146 6962074 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter/Conference proceeding › Conference proceeding › Academic › peer-review

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AB - Reconfigurable hardware can be employed to tolerate permanent faults. Hardware components comprising a System-on-Chip can be partitioned into a handful of substitutable units interconnected with reconfigurable wires to allow isolation and replacement of faulty parts. This paper offers a probabilistic analysis of reconfigurable designs estimating for different fault densities the average number of fault-free components that can be constructed as well as the probability to guarantee a particular availability of components. Considering the area overheads of reconfigurability, we evaluate the resilience of various reconfigurable designs with different granularities. Based on this analysis, we conduct a comprehensive design-space exploration to identify the granularity mixes that maximize the fault-tolerance of a system. Our findings reveal that mixing fine-grain logic with a coarse-grain sparing approach tolerates up to 3× more permanent faults than component redundancy and 2× more than any other purely coarse-grain solution. Component redundancy is preferable at low fault densities, while coarse-grain and mixed-grain reconfigurability maximize availability at medium and high fault densities, respectively.

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Malek A, Tzilis S, Khan DA, Sourdis I, Smaragdos G , Strydis C. A probabilistic analysis of resilient reconfigurable designs. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc. 2014. p. 141-146. 6962074. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). doi: 10.1109/DFT.2014.6962074

A probabilistic analysis of resilient reconfigurable designs

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