PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems

Carlos Salazar-Garcia, Jeferson Gonzalez-Gomez, Kaleb Alfaro-Badilla, Ronny Garcia-Ramirez, Renato Rimolo-Donadio, Christos Strydis, Alfonso Chacon-Rodriguez

Research output: Chapter/Conference proceedingConference proceedingAcademicpeer-review

1 Citation (Scopus)

Abstract

This paper presents preliminary results of Plastic-Net, a custom FPGA interconnect architecture designed for high-processing applications that communicate extensively among multiple FPGAs. PlasticNet allows the interconnection of processing nodes (PNs) through a flexible, reliable and efficient custom protocol, that can be easily integrated in High-Level Synthesis (HLS) modern design environments. The system is evaluated on a ZedBoard Zynq®-7000 ARM/FPGA SoC Development Board, including criteria such as overhead, area, worst-case packet delivery latency and bandwidth. The best evaluated case achieved a half-occupancy latency of 16.9μs. The results show the potential of PlasticNet as an efficient solution for low latency multi-FPGA interconnection.

Original languageEnglish
Title of host publicationPRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728131467
DOIs
Publication statusPublished - Feb 2020
Event3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020 - San Jose, Costa Rica
Duration: 25 Feb 202028 Feb 2020

Publication series

SeriesPRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings

Conference

Conference3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020
Country/TerritoryCosta Rica
CitySan Jose
Period25/02/2028/02/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

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