PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems

Carlos Salazar-Garcia; Jeferson Gonzalez-Gomez; Kaleb Alfaro-Badilla; Ronny Garcia-Ramirez; Renato Rimolo-Donadio; Christos Strydis; Alfonso Chacon-Rodriguez

doi:10.1109/PRIME-LA47693.2020.9062749

PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems

Carlos Salazar-Garcia, Jeferson Gonzalez-Gomez, Kaleb Alfaro-Badilla, Ronny Garcia-Ramirez, Renato Rimolo-Donadio, Christos Strydis, Alfonso Chacon-Rodriguez

Neurosciences

Research output: Chapter/Conference proceeding › Conference proceeding › Academic › peer-review

2 Citations (Scopus)

Abstract

This paper presents preliminary results of Plastic-Net, a custom FPGA interconnect architecture designed for high-processing applications that communicate extensively among multiple FPGAs. PlasticNet allows the interconnection of processing nodes (PNs) through a flexible, reliable and efficient custom protocol, that can be easily integrated in High-Level Synthesis (HLS) modern design environments. The system is evaluated on a ZedBoard Zynq®-7000 ARM/FPGA SoC Development Board, including criteria such as overhead, area, worst-case packet delivery latency and bandwidth. The best evaluated case achieved a half-occupancy latency of 16.9μs. The results show the potential of PlasticNet as an efficient solution for low latency multi-FPGA interconnection.

Original language	English
Title of host publication	PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728131467
DOIs	https://doi.org/10.1109/PRIME-LA47693.2020.9062749
Publication status	Published - Feb 2020
Event	3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020 - San Jose, Costa Rica Duration: 25 Feb 2020 → 28 Feb 2020

Publication series

Series	PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings

Conference

Conference	3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020
Country/Territory	Costa Rica
City	San Jose
Period	25/02/20 → 28/02/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Access to Document

10.1109/PRIME-LA47693.2020.9062749

Cite this

Salazar-Garcia, C., Gonzalez-Gomez, J., Alfaro-Badilla, K., Garcia-Ramirez, R., Rimolo-Donadio, R., Strydis, C., & Chacon-Rodriguez, A. (2020). PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems. In PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings Article 9062749 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME-LA47693.2020.9062749

Salazar-Garcia, Carlos ; Gonzalez-Gomez, Jeferson ; Alfaro-Badilla, Kaleb et al. / PlasticNet : A low latency flexible network architecture for interconnected multi-FPGA systems. PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings).

@inproceedings{19fc2a60ef9442339f35976bede001d4,

title = "PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems",

abstract = "This paper presents preliminary results of Plastic-Net, a custom FPGA interconnect architecture designed for high-processing applications that communicate extensively among multiple FPGAs. PlasticNet allows the interconnection of processing nodes (PNs) through a flexible, reliable and efficient custom protocol, that can be easily integrated in High-Level Synthesis (HLS) modern design environments. The system is evaluated on a ZedBoard Zynq{\textregistered}-7000 ARM/FPGA SoC Development Board, including criteria such as overhead, area, worst-case packet delivery latency and bandwidth. The best evaluated case achieved a half-occupancy latency of 16.9μs. The results show the potential of PlasticNet as an efficient solution for low latency multi-FPGA interconnection.",

author = "Carlos Salazar-Garcia and Jeferson Gonzalez-Gomez and Kaleb Alfaro-Badilla and Ronny Garcia-Ramirez and Renato Rimolo-Donadio and Christos Strydis and Alfonso Chacon-Rodriguez",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020 ; Conference date: 25-02-2020 Through 28-02-2020",

year = "2020",

month = feb,

doi = "10.1109/PRIME-LA47693.2020.9062749",

language = "English",

series = "PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings",

booktitle = "PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

}

Salazar-Garcia, C, Gonzalez-Gomez, J, Alfaro-Badilla, K, Garcia-Ramirez, R, Rimolo-Donadio, R, Strydis, C & Chacon-Rodriguez, A 2020, PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems. in PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings., 9062749, Institute of Electrical and Electronics Engineers Inc., PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings, 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020, San Jose, Costa Rica, 25/02/20. https://doi.org/10.1109/PRIME-LA47693.2020.9062749

PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems. / Salazar-Garcia, Carlos; Gonzalez-Gomez, Jeferson; Alfaro-Badilla, Kaleb et al.
PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9062749 (PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings).

Research output: Chapter/Conference proceeding › Conference proceeding › Academic › peer-review

TY - GEN

T1 - PlasticNet

T2 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020

AU - Salazar-Garcia, Carlos

AU - Gonzalez-Gomez, Jeferson

AU - Alfaro-Badilla, Kaleb

AU - Garcia-Ramirez, Ronny

AU - Rimolo-Donadio, Renato

AU - Strydis, Christos

AU - Chacon-Rodriguez, Alfonso

PY - 2020/2

Y1 - 2020/2

N2 - This paper presents preliminary results of Plastic-Net, a custom FPGA interconnect architecture designed for high-processing applications that communicate extensively among multiple FPGAs. PlasticNet allows the interconnection of processing nodes (PNs) through a flexible, reliable and efficient custom protocol, that can be easily integrated in High-Level Synthesis (HLS) modern design environments. The system is evaluated on a ZedBoard Zynq®-7000 ARM/FPGA SoC Development Board, including criteria such as overhead, area, worst-case packet delivery latency and bandwidth. The best evaluated case achieved a half-occupancy latency of 16.9μs. The results show the potential of PlasticNet as an efficient solution for low latency multi-FPGA interconnection.

AB - This paper presents preliminary results of Plastic-Net, a custom FPGA interconnect architecture designed for high-processing applications that communicate extensively among multiple FPGAs. PlasticNet allows the interconnection of processing nodes (PNs) through a flexible, reliable and efficient custom protocol, that can be easily integrated in High-Level Synthesis (HLS) modern design environments. The system is evaluated on a ZedBoard Zynq®-7000 ARM/FPGA SoC Development Board, including criteria such as overhead, area, worst-case packet delivery latency and bandwidth. The best evaluated case achieved a half-occupancy latency of 16.9μs. The results show the potential of PlasticNet as an efficient solution for low latency multi-FPGA interconnection.

UR - http://www.scopus.com/inward/record.url?scp=85084039882&partnerID=8YFLogxK

U2 - 10.1109/PRIME-LA47693.2020.9062749

DO - 10.1109/PRIME-LA47693.2020.9062749

M3 - Conference proceeding

AN - SCOPUS:85084039882

T3 - PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings

BT - PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 25 February 2020 through 28 February 2020

ER -

Salazar-Garcia C, Gonzalez-Gomez J, Alfaro-Badilla K, Garcia-Ramirez R, Rimolo-Donadio R, Strydis C et al. PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems. In PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9062749. (PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings). doi: 10.1109/PRIME-LA47693.2020.9062749

PlasticNet: A low latency flexible network architecture for interconnected multi-FPGA systems

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Other files and links

Fingerprint

Cite this